The present invention is related to electronic signal conversion, and more particularly to pipelined analog to digital converters.
Pipelined analog to digital converters exist, but often offer complex and sometimes unsolvable timing problems. In particular, existing pipelined analog to digital converters often have difficult to meet residue amplifier gain-bandwidth requirements.
Pipelined analog to digital converters exist that use a sampling capacitor charged on one phase of a clock, and a corresponding feedback capacitor that is charged on the opposite phase of the clock. The sampling capacitor stores the analog to digital converter input minus the coarse digital to analog converter output. An example of a portion of one such analog to digital converter is depicted in FIG. 1. Turning to FIG. 1, a differential analog to digital converter 100 including a sampling capacitor (the additive combination of parallel capacitors C1n-C4n and C1p-C4p) is shown. Sampling capacitors C1n-C4n are each selectably connected to either a positive side of a differential analog voltage input 120, a positive reference voltage 122 or a negative reference voltage 124 via switches 126. Similarly, sampling capacitors C1p-C4p are each selectably connected to either a negative side of a differential analog voltage input 121, positive reference voltage 122 or negative reference voltage 124 via switches 128. In operation during a first clock phase (i.e., Φ1), all sampling capacitors (C1n, C2n, C3n, C4n, C1p, C2p, C3p, C4p) are connected between inputs of an operational amplifier 110 and an analog voltage input (i.e., positive input 120 or negative input 121). Also, operational amplifier 110 is connected with unity gain feedback. The capacitor charge at the end of the first clock phase is therefore:QC1P=QC2P=QC3P=QC4P=QC1N=QC2N=QC3N=QC4N.During a second clock phase (i.e., Φ2), feedback capacitors 130 are connected from respective legs of a differential output 140 to respective inputs 145 of operational amplifier 110. At the same time, the sampling capacitors (C1n, C2n, C3n, C4n, C1p, C2p, C3p, C4p) are connected between a selected reference voltage (either +Vref or −Vref) and the operational amplifier inputs 145. In some configurations the feedback capacitors are discharged rather than being connected to the input. During this phase (i.e., Φ2), the residue is calculated as the difference between Vin and the MDAC output. Both operations of sampling and resolving the residue are performed in sequence during a single clock cycle consisting of two substantially equal periods (i.e., Φ1 and Φ2). Usually, one half of the clock period is allowed for sampling the input (i.e., Φ1), and the remaining one half clock period is used for computing the residue (i.e., Φ2). This approach limits the time budget for resolving any residue, and hence increases the required operational bandwidth of the circuit implementing such an approach.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems, circuits and methods for electronic signal conversion.